Design of reconfigurable RF circuits for self compensation

In this paper we will show how a combination of design choices allows for the design of a PVT robust RF front-end with minimum area, power and nominal specifications penalty.Peer ReviewedPostprint (published version

Differential temperature sensors: Review of applications in the test and characterization of circuits, usage and design methodology

Differential temperature sensors can be placed in integrated circuits to extract a signature ofthe power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper firstdiscusses the singularity that differential temperature sensors provide with respect to other sensortopologies, with circuit monitoring being their main application. The paper focuses on the monitoringof radio-frequency analog circuits. The strategies to extract the power signature of the monitoredcircuit are reviewed, and a list of application examples in the domain of test and characterizationis provided. As a practical example, we elaborate the design methodology to conceive, step bystep, a differential temperature sensor to monitor the aging degradation in a class-A linear poweramplifier working in the 2.4 GHz Industrial Scientific Medical—ISM—band. It is discussed how,for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamicrange is required. A circuit solution for this objective is proposed, as well as recommendations for thedimensions and location of the devices that form the temperature sensor. The paper concludes with adescription of a simple procedure to monitor time variability.Postprint (published version

Implementation of a 5x5 trits multiplier in a quasi-adiabatic ternary CMOS logic

© 1997 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Adiabatic switching is one technique to design low power digital IC. In order to diminish its expensive silicon area requirements an adiabatic ternary logic is proposed. A 5×5 trits (ternary signals) multiplier has been designed and implemented using this logic in a 0.7µm CMOS technology. Results show a satisfactory power saving and a decreasing of the area needed with respect to an adiabatic binary one.Peer ReviewedPostprint (published version

Thermal coupling in ICs: aplications to the test and characterization of analogue and RF circuits

In this presentation we cover how to use low frequency or DC temperature measurements to observe figures of merit of high frequency analogue circuits.Postprint (published version

Electro-thermal coupling analysis methodology for RF circuits

In this paper we present an electro-thermal coupling simulation technique for RF circuits. The proposed methodology takes advantage of well established tools for frequency translating circuits in order to significantly reduce the computational resources needed when frequencies of interest are separated by orders of magnitude.Postprint (published version

Desenvolupament d'un sistema de comunicacions integrat per part d'estudiants de 2on cicle de l'ETSETB de la Universitat Politècnica de Catalunya

El projecte ha consistit en el disseny i fabricació d’un circuit integrat que conté un receptor Bluetooth per a xarxes sense fils en una tecnologia CMOS de 0,35 m. Els objectius del projecte eren realitzar una experiència de treball tutelat en el camp del disseny de circuits integrats avançats per part d’estudiants de 2on. cicle de l’ETSETB a través del qual poguessin aplicar els coneixements adquirits en diferents assignatures a un projecte comú, alhora que aprenien a fer servir les eines i els procediments de disseny professionals en l’àmbit dels circuits microelectrònics. La peculiaritat de la metodologia és que els estudiants hi han treballat de forma voluntària durant l’horari no lectiu, tot i que aquesta activitat se’ls ha reconegut com crèdits ALE. Primer han hagut d’aprendre a fer servir les eines de disseny mitjançant uns tutorials d’autoaprenentatge desenvolupats pels professors i més tard s’enfrontaven al disseny i realització de sub-blocs senzills del disseny global. El treball dels estudiants ha fet possible el disseny d’un receptor integrat complert en un temps d’uns 12 mesos que s’acaba d’enviar a fabricar

DLL's behavioral modeling for power consumption and jitter fast optimization

This paper analyzes the sources of jitter in a DLL and presents a behavioral model for fast DLL optimization. An algorithm to simulate the DLL in open loop is demonstrated. This procedure, together with the behavioral modeling, greatly reduces the simulation time of DLL when compared to the closeloop DLL simulation. In order to optimize the DLL performance, the dependence of the output jitter versus the power consumption is studied.Postprint (author’s final draft

Providing an UWB-IR BAN wireless communications network and its application to design a low power transceiver in CMOS technology

Ultra Wide-Band (UWB) communication techniques have received increasing attention since United States Federal Communications Commission (FCC) adopted a “First Report and Order” in 2002. Unfortunately the regulations that appeared a few years latter didn't have the same level of commitment and had much tighter constraints. The FCC part. 15 power spectral density limitation is depicted. Although the word-wide common bandwidth is quite scarce (7.25 to 8.5 GHz), UWB still has its niche applications. Impulse Radio (IR) implementation of UWB systems has very interesting features such as low complexity, low power consumption, low cost, high data-rate, and the ability of coexistence with other radio systems.Peer ReviewedPostprint (published version

CATRENE-PANAMA WP1: integrated PA Milestone M1.3 technology, approach & system choice for home networking

Preprin

An approach to dynamic power consumption current testing of CMOS ICs

© 1995 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.I/sub DDQ/ testing is a powerful strategy for detecting defects that do not alter the logic behavior of CMOS ICs. Such a technique is very effective especially in the detection of bridging defects although some opens can be also detected. However, an important set of open and parametric defects escape quiescent power supply current testing because they prevent current elevation. Extending the consumption current testing time, from the static period to the dynamic one (i.e. considering the transient current), defects not covered with I/sub DDQ/ can be detected. Simulations using an on-chip sensor show that this technique can reach a high coverage for defects preventing current and also for those raising the static power consumption.Peer ReviewedPostprint (published version